Charge control that keeps constant input voltage supplied to battery pack

ABSTRACT

A circuit for controlling charging includes a transistor provided on a charging path between a position of a charging terminal and a position of a battery, an input voltage detecting circuit configured to detect a potential of a point on the charging path coupled to the charging terminal&#39;s side of the transistor, and a drive circuit configured to control an ON resistance of the transistor between a conductive state and a nonconductive state in response to the potential detected by the input voltage detecting circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priorityfrom the prior Japanese Patent Application No. 2004-175721 filed on Jun.14, 2004, with the Japanese Patent Office, the entire contents of whichare incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to charging circuits used inbattery packs for electronic apparatus, and also relates to such batterypacks and electronic apparatus. The present invention particularlyrelates to a charge control circuit for controlling the charging of abattery in the battery pack of electronic apparatus, and also relates tosuch a battery pack and electronic apparatus.

2. Description of the Related Art

In portable apparatus such as notebook-type personal computers or thelike, an internal power supply circuit for supplying electric power tocore electronic circuitry is required to be small. The internal powersupply circuit is also required to be operable with high efficiency inorder to achieve a long battery-powered operating time.

Notebook personal computers use a battery pack or an AC adapterreceiving power from a commercial power supply as the source of electricpower. A predetermined voltage (e.g., 16 V) supplied from this source ofelectric power is converted to other voltage levels by an internal powersupply circuit, thereby supplying internal voltages needed by respectivecore electronic circuits. For example, CPU uses a voltage level of 0.9 Vor 1.5 V, a hard-disc drive and CD-ROM drive using 5 V, an LSI using 3.3V, and a memory using 2.5 V. In order to charge the battery pack, the16-V voltage level output from the AC adapter is lowered to 12.6 V by acharger, and this lowered voltage is supplied to the battery pack suchas a lithium-ion battery pack. When the commercial power supply is notused, the battery pack charged in this manner is used to supply electricpower to the internal power supply circuit.

As the circuit density of semiconductor integrated circuits increases,with resultant improvement in functionality and performance, theoperating voltage of semiconductor integrated circuits is increasinglylowered. With such lowering of an operating voltage, an internal powersupply circuit provided inside notebook personal computers or the likeneeds to make a significant voltage reduction to a predetermined voltagesupplied from an AC adaptor in order to produce a stepped-down voltagethat is to be supplied to core electronic circuitry.

A DC-DC converter serving as the internal power supply circuit, however,has a problem in that efficiency drops as a difference between the inputvoltage and the output voltage widens. An on/off ratio of the outputtransistor of a DC-DC converter is determined according to a ratio ofthe output voltage to the input voltage. As a difference between theinput voltage and the output voltage widens, therefore, the “on” periodof the output transistor becomes extremely short. As a result, the timelength of a rise and a fall of the output transistor ends up having asignificant proportion relative to the time length of the “on” period,resulting in voltage conversion efficiency deteriorating. When the “on”period of the output transistor becomes extremely short, also, itbecomes difficult to increase the frequency of a DC-DC converter.Because of this, there is no choice but to use the DC-DC converter atlow operating frequency, which ends up requiring a bulky coil. This isnot preferable when considering the miniaturization of a DC-DCconverter.

The above-stated problems are obviated if a difference between the inputvoltage and output voltage of a DC-DC converter is reduced. The outputof an AC adaptor, which also serves as the source of electric power,cannot be lowered below a predetermined level (e.g., 16 V) because thisoutput is also used to drive the display of the notebook personalcomputer. Against this background, proposals have been made to utilize avoltage level of 12.6 V output from the charger as described above as aninput to a DC-DC converter.

FIG. 1 is a block diagram showing an example of the construction of asystem supplying the output of a charger to a DC-DC converter. In FIG.1, an AC adapter 10 receives an alternating voltage (e.g., 100. V) froma commercial power supply or the like, and generates a direct-currentvoltage (e.g., 16 V) for provision to a charger 11. The charger 11generates a predetermined voltage (12.6 V) from the voltage suppliedfrom the AC adapter 10. The generated voltage is supplied as a chargevoltage V+ to a battery pack 13 through a current detecting resistor 14,which provides charging to be performed with a constant current. Thepredetermined voltage (12.6 V) output from the charger 11 is alsosupplied to a DC-DC converter 12 where it is converted to other voltagelevels. Then, the stepped-down voltages (e.g., 0.9 V, 2.5 V, 3.3 V, 5.0V) are supplied to respective internal electronic circuits.

The battery pack 13 includes a PMOS transistor 21, a PMOS transistor 22,an overcharge and over-discharge detecting circuit 23, and a lithium-ionbattery 24. In this example, the lithium-ion battery 24 has aconstruction in which three batteries are connected in series. Theovercharge and over-discharge detecting circuit 23 measures the voltagelevel of the lithium-ion battery 24 to detect whether it is in anovercharged state or in an over-discharged state. Upon detecting anovercharged stage, the overcharge and over-discharge detecting circuit23 provides a HIGH overcharge detection signal to the gate of the PMOStransistor 21. In response, the PMOS transistor 21 becomesnonconductive, thereby preventing further charging. If anover-discharged state is detected, the overcharge and over-dischargedetecting circuit 23 provides a HIGH over-discharge detection signal tothe gate of the PMOS transistor 22. In response, the PMOS transistor 22becomes nonconductive, thereby preventing further discharging.

In the construction of FIG. 1, the input voltage supplied to the DC-DCconverter 12 is not the output voltage (e.g., 16 V) of the AC adapter 10but the stepped-down voltage (e.g., 12.6 V) lowered by the charger 11.Since a difference between the output voltage and input voltage of theDC-DC converter 12 is not so large, advantage is gained in terms ofvoltage conversion efficiency and circuit size.

(Patent Document 1] Japanese Patent Application Publication No.2002-10509

In the construction of FIG. 1, the input voltage of the DC-DC converter12 is clamped to the input voltage V+ of the battery pack 13. When theinput voltage V+ of the battery pack 13 drops in an over-dischargedstate, the input voltage of the DC-DC converter 12 also drops. If thevoltage V+ falls below 5 V in the over-discharged stage, the DC-DCconverter 12 cannot supply an output voltage of 5 V to the coreelectronic circuitry.

Moreover, since the charger 11 is a DC-DC converter operating based onconstant-current and constant-voltage control, its output voltagefluctuate (drops) if the electric-current load exceeds a specifiedlevel. If the load of the DC-DC converter 12 increases while the batterypack 13 is charged, the voltage V+ equal to the output of the charger 11fluctuates (drops). This may cause a failure with respect to theoperation of the DC-DC converter 12 and the charging of the battery pack13.

Accordingly, there is a need for a charge control circuit that controlsa charging process such as to keep constant the input voltage V+ of abattery pack of electronic apparatus. There is also a need for such abattery pack and electronic apparatus.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a chargecontrol circuit, a battery pack, and an electronic apparatus thatsubstantially obviate one or more problems and drawbacks caused by thelimitations and disadvantages of the related art.

Features and advantages of the present invention will be presented inthe description which follows, and in part will become apparent from thedescription and the accompanying drawings, or may be learned by practiceof the invention according to the teachings provided in the description.Objects as well as other features and advantages of the presentinvention will be realized and attained by a charge control circuit, abattery pack, and an electronic apparatus particularly pointed out inthe specification in such full, clear, concise, and exact terms as toenable a person having ordinary skill in the art to practice theinvention.

To achieve these and other advantages in accordance with the purpose ofthe invention, the invention provides a circuit for controllingcharging, which includes a transistor provided on a charging pathbetween a position of a charging terminal and a position of a battery,an input voltage detecting circuit configured to detect a potential of apoint on the charging path coupled to the charging terminal's side ofthe transistor, and a drive circuit configured to control an ONresistance of the transistor between a conductive state and anonconductive state in response to the potential detected by the inputvoltage detecting circuit.

According to another aspect of the invention, a battery pack includes acharge control circuit and a battery configured to be charged through acharging path, wherein the charge control circuit includes a transistorprovided on the charging path between a position of a charging terminaland a position of the battery, an input voltage detecting circuitconfigured to detect a potential of a point on the charging path coupledto the charging terminal's side of the transistor, and a drive circuitconfigured to control an ON resistance of the transistor between aconductive state and a nonconductive state in response to the potentialdetected by the input voltage detecting circuit.

According to another aspect of the invention, an electronic apparatusincludes a battery pack including a charge control circuit and a batteryconfigured to be charged through a charging path, a charger having aninput terminal receiving a direct-current voltage and an output terminalcoupled to the battery pack, and configured step down the direct-currentvoltage received at the input terminal for output to the outputterminal, a DC-DC converter coupled to the output terminal of thecharger, and an electronic circuit coupled to an output of the DC-DCconverter, wherein the charge control circuit includes a transistorprovided on the charging path between a position of a charging terminaland a position of the battery, an input voltage detecting circuitconfigured to detect a potential of a point on the charging path coupledto the charging terminal's side of the transistor, and a drive circuitconfigured to control an ON resistance of the transistor between aconductive state and a nonconductive state in response to the potentialdetected by the input voltage detecting circuit.

According to at least one embodiment of the invention, the ON resistanceof the transistor is controlled in response to the input voltagesupplied to the charging terminal in such manner that the ON resistancetakes any value between a fully conductive state and a fullynon-conductive state. In the related-art construction, the control of atransistor uses only two states, i.e., an “on” state or an “off” state.In at least one embodiment of the invention, the control of thetransistor is performed continuously between the “on” state and the“off” state. This makes it possible to achieve feedback control thatstabilizes the input voltage at a predetermined voltage level.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and further features of the present invention will beapparent from the following detailed description when read inconjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing an example of the construction of asystem supplying the output of a charger to a DC-DC converter;

FIG. 2 is a circuit diagram showing the construction of a firstembodiment of a charge control circuit according to the presentinvention;

FIG. 3 is a diagram for explaining the charging operation of the chargecontrol circuit shown in FIG. 2;

FIG. 4 is a circuit diagram showing the construction of a secondembodiment of the charge control circuit according to the presentinvention;

FIG. 5 is a circuit diagram showing the construction of a thirdembodiment of the charge control circuit according to the presentinvention;

FIG. 6 is a circuit diagram showing the construction of a fourthembodiment of the charge control circuit according to the presentinvention;

FIG. 7 is a circuit diagram showing the construction of a fifthembodiment of the charge control circuit according to the presentinvention; and

FIG. 8 is a circuit diagram showing the construction of a sixthembodiment of the charge control circuit according to the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments of the present invention will be describedwith reference to the accompanying drawings.

FIG. 2 is a circuit diagram showing the construction of a firstembodiment of a charge control circuit according to the presentinvention. The charge control circuit of FIG. 2 includes an inputvoltage detecting circuit 31 and a drive circuit 32 as main elements,and is provided in the battery pack 13 shown in FIG. 1.

The input voltage detecting circuit 31 includes resistors R1 and R2, anamplifier 35, and a reference-voltage source 36. The drive circuit 32includes an NMOS transistor 37. In the input voltage detecting circuit31, the input voltage V+ of the battery pack 13 is divided by theresistors R1 and R2, and a divided potential VA is supplied to thenon-inverted input terminal of the amplifier 35. The inverted inputterminal of the amplifier 35 receives a reference potential from thereference-voltage source 36. The amplifier 35 generates an outputresponsive to a difference between the divided potential VA and thereference potential for provision to the gate node of the NMOStransistor 37 of the drive circuit 32. The drain node of the NMOStransistor 37 is connected to the gate node of the PMOS transistor 21.

With this provision, a potential at the gate node of the PMOS transistor21 is controlled according to the level of the input voltage V+. As theinput voltage V+ increases, the output potential of the amplifier 35rises, resulting in a drop in the gate potential of the PMOS transistor21. This reduces the ON resistance of the PMOS transistor 21. Since thecharger 11 (see FIG. 1) performs constant-current charging by use of thecurrent detecting resistor 14, a drop in the ON resistance of the PMOStransistor 21 causes a drop in the input voltage V+. In this manner, theinput voltage V+ is controlled to drop in response to an increase in theinput voltage V+, thereby settling at a predetermined voltage.

Conversely, a drop in the input voltage V+ results in a drop in theoutput potential of the amplifier 35, thereby raising the gate potentialof the PMOS transistor 21. This increases the ON resistance of the PMOStransistor 21. Since the charger 11 (see FIG. 1) performsconstant-current charging by use of the current detecting resistor 14,an increase in the ON resistance of the PMOS transistor 21 causes a risein the input voltage V+. In this manner, the input voltage V+ iscontrolled to rise in response to a drop in the input voltage V+,thereby settling at a predetermined voltage.

In this manner, the present invention controls the ON resistance of thePMOS transistor 21 in response to the input voltage V+ such that the ONresistance takes any value between a fully conductive state and a fullynon-conductive state. In the related-art construction shown in FIG. 1,the control of the PMOS transistor 21 uses only two states, i.e., an“on” state or an “off” state. In the present invention, the control ofthe PMOS transistor 21 is performed continuously between the “on” stateand the “off” state. This makes it possible to achieve feedback controlthat stabilizes the input voltage V+ at a predetermined voltage level.

At the time of overcharging, the overcharge detecting signal changes toHIGH, making the NMOS transistor 33 conductive. This makes the NMOStransistor 37 of the drive circuit 32 nonconductive, so that the gate ofthe PMOS transistor 21 coupled to the input voltage V+ through aresistor R0 changes to HIGH. As a result, the PMOS transistor 21 becomesnonconductive, suspending charging. Although the PMOS transistor 21 forcharge control is nonconductive at the time of overcharging, a parasiticdiode 34 permits discharging.

FIG. 3 is a diagram for explaining the charging operation of the chargecontrol circuit shown in FIG. 2. In FIG. 3, the horizontal axisrepresents time t. As a charging operation continues, the batteryvoltage of the lithium-ion battery 24 gradually goes up. To cancel sucha voltage rise, a charge control operation by the input voltagedetecting circuit 31 and the drive circuit 32 lowers the gate voltageand ON resistance Ron of the PMOS transistor 21. With this, the DSvoltage that is a voltage between the drain and source of the PMOStransistor 21 gradually drops.

FIG. 4 is a circuit diagram showing the construction of a secondembodiment of the charge control circuit according to the presentinvention. In FIG. 4, the same elements as those of FIG. 2 are referredto by the same numerals, and a description thereof will be omitted.

A charge control circuit of FIG. 4 includes an NMOS transistor 40 inaddition to the construction of the charge control circuit of FIG. 2.The NMOS transistor 40 receives a standby signal at its gate node, andcouples the gate node of the PMOS transistor 21 to a ground when astandby signal is HIGH. This standby signal becomes HIGH when the loadof a power supply is small in an apparatus to which the battery pack 13is attached. If the apparatus to which the battery pack 13 is attachedis a notebook personal computer, for example, the load of a power supplyis small in the standby mode of the notebook personal computer sinceoperations are suspended in most of the core electronic circuits. Inthis standby mode, the standby signal becomes HIGH, thereby coupling thegate node of the PMOS transistor 21 to a ground and thus making the PMOStransistor 21 fully conductive.

In the second embodiment shown in FIG. 4, the PMOS transistor 21 isfully turned on when the load of a power supply (i.e., the load of thecharger 11) is small, thereby achieving a charging process with amassive current. This makes it possible to shorten a charge time.

FIG. 5 is a circuit diagram showing the construction of a thirdembodiment of the charge control circuit according to the presentinvention. In FIG. 5, the same elements as those of FIG. 2 are referredto by the same numerals, and a description thereof will be omitted.

A charge control circuit of FIG. 5 includes a current detecting resistorRs and a current detector 50 in addition to the construction of thecharge control circuit of FIG. 2. With the provision of the currentdetector 50, the drive circuit 32 is changed to a drive circuit 32A.Since the gate node of the NMOS transistor 37 of the drive circuit 32Ais connected to the output of the current detector 50, the output of theamplifier 35 of an input voltage detecting circuit 31A is coupled to thegate node of the NMOS transistor 37 via an NMOS transistor 38intervening therebetween. Due to this change, further, the invertedinput terminal and non-inverted input terminal of the amplifier 35 areswitched with each other.

The current detector 50 includes an amplifier 51 and a reference-voltagesource 52. A voltage responsive to a current flowing through thelithium-ion battery 24 is generated as voltage VB at one end of thecurrent detecting resistor Rs. This potential VB is supplied to aninverted input terminal of the amplifier 51. The non-inverted inputterminal of the amplifier 51 receives a reference potential from thereference-voltage source 52. The amplifier 51 generates an outputresponsive to a difference between the potential VB and the referencepotential for provision to the gate node of the NMOS transistor 37 ofthe drive circuit 32A. The drain node of the NMOS transistor 37 isconnected to the gate node of the PMOS transistor 21. The gate node ofthe NMOS transistor 37 is further connected to the drain node of theNMOS transistor 38.

As a charge current increases, the voltage VB proportional to the chargecurrent goes up, resulting in a drop in the output voltage of theamplifier 51. In response, the gate potential of the PMOS transistor 21rises, thereby increasing the ON resistance of the PMOS transistor 21.This causes the charge current to decrease. In this manner the chargecurrent is controlled to drop in response to an increase in the chargecurrent, thereby settling at a predetermined current amount.

As a charge current decreases, the voltage VB proportional to the chargecurrent goes down, resulting in a rise in the output voltage of theamplifier 51. In response, the gate potential of the PMOS transistor 21falls, thereby decreasing the ON resistance of the PMOS transistor 21.This causes the charge current to increase. In this manner the chargecurrent is controlled to rise in response to a drop in the chargecurrent, thereby settling at a predetermined current amount.

In the embodiment describe above, the current detector 50 detects acharge current running through the lithium-ion battery 24, and the drivecircuit 32A controls the ON resistance of the PMOS transistor 21 inresponse to the detected charge current. This eliminates a need for theconstant-current-based control of the charger 11. Further, the inputvoltage detecting circuit 31A detects the input voltage V+, and thedrive circuit 32A controls the ON resistance of the PMOS transistor 21in response to the detected input voltage V+. This makes it possible tokeep constant the input voltage V+ as in the first embodiment.

FIG. 6 is a circuit diagram showing the construction of a fourthembodiment of the charge control circuit according to the presentinvention. In FIG. 6, the same elements as those of FIG. 2 are referredto by the same numerals, and a description thereof will be omitted.

A charge control circuit of FIG. 6 includes a differential amplificationcircuit 61, a multiplication circuit 62, a current monitoring circuit63, an amplifier 64, an NMOS transistor 65, and a current detectingresistor Rs in addition to the construction of the charge controlcircuit of FIG. 2. Further, an input voltage detecting circuit 31A isprovided in place of the input voltage detecting circuit 31. In theinput voltage detecting circuit 31A, the inverted input terminal andnon-inverted input terminal of the amplifier 35 are switched with eachother compared to the amplifier 35 of the input voltage detectingcircuit 31.

The differential amplification circuit 61 includes resistors R3 throughR6 and an amplifier 67. The non-inverted input terminal of the amplifier67 receives a potential that is obtained by dividing the input voltageV+ of the battery pack 13 by the resistor R5 and the resistor R6. Theinverted input terminal of the amplifier 67 receives a potentialresponsive to the potential VB appearing at one end of the PMOStransistor 21. The potential VB is a potential appearing on the oppositeside to the V+ side among the source node and drain node of the PMOStransistor 21. With this provision, the amplifier 67 outputs a potentialresponsive to a difference between V+ and VB, i.e., a potentialresponsive to a voltage drop across the PMOS transistor 21. The outputof the amplifier 67 is supplied to the multiplication circuit 62.

The multiplication circuit 62 includes resistors R7 through R10,transistors Q1 through Q6, voltage sources V1 and V2, and a constantcurrent source 68. As described above, the potential responsive to adifference between V+ and VB is input into the multiplication circuit 62from the amplifier 67 of the differential amplification circuit 61.Further, the multiplication circuit 62 receives a potential responsiveto a charge current IRS from the amplifier 69 of the current monitoringcircuit 63. The amplifier 69 detects a voltage drop produced by thecharge current IRS flowing through the current detecting resistor Rs.The multiplication circuit 62 obtains a product of the charge currentIRS and the potential difference between V+ and VB so as to calculateelectric power consumed by the PMOS transistor 21. An output VC of themultiplication circuit 62 indicative of this electric power is suppliedto the inverted input terminal of the amplifier 64. The non-invertedinput terminal of the amplifier 64 is connected to a reference-voltagesource VTH2.

As the electric power VC consumed at the PMOS transistor 21 increases,the output of the amplifier 64 drops, resulting in a rise in the gatevoltage of the PMOS transistor 21. Consequently, the ON resistance ofthe PMOS transistor 21 increases, thereby decreasing the charge current.As the electric power VC consumed at the PMOS transistor 21 decreases,the output of the amplifier 64 rises, resulting in a drop in the gatevoltage of the PMOS transistor 21. Consequently, the ON resistance ofthe PMOS transistor 21 decreases, thereby increasing the charge current.

With this provision, it is possible to keep constant the electric powerconsumed at the PMOS transistor 21, thereby suppressing excess heatgeneration at the PMOS transistor 21. Further, the input voltage V+ iskept constant in the same manner as in the first embodiment shown inFIG. 2. In the fourth embodiment shown in FIG. 6, the gate node of theNMOS transistor 37 of the drive circuit 32 is connected to the output ofthe amplifier 64, the output of the amplifier 35 of the input voltagedetecting circuit 31A is coupled to the gate node of the NMOS transistor37 via an NMOS transistor 65 intervening therebetween. Due to thischange, further, the inverted input terminal and non-inverted inputterminal of the amplifier 35 are switched with each other.

Moreover, the circuit construction of the multiplication circuit 62 isillustrated as an example, and is not intended to be limiting. Anycircuit construction may be used as long as it achieves a multiplicationfunction.

FIG. 7 is a circuit diagram showing the construction of a fifthembodiment of the charge control circuit according to the presentinvention. In FIG. 7, the same elements as those of FIG. 4 are referredto by the same numerals, and a description thereof will be omitted.

In addition to the construction of the charge control circuit of FIG. 4,a charge control circuit of FIG. 7 includes a PMOS transistor 71, aparasitic diode 72, and resistors R11 and R12. Moreover, the output ofthe drive circuit 32 is supplied to the gate node of the PMOS transistor71 for the precharge purpose rather than to the gate node of the PMOStransistor 21.

During a normal charging process, the PMOS transistor 21 is in anonconductive state. In this case, the input voltage detecting circuit31 and the drive circuit 32 control the ON resistance of the PMOStransistor 71 in such manner that the ON resistance may take any valuebetween the conductive state and the nonconductive state, therebycharging the lithium-ion battery 24 while keeping the input voltage V+constant. When the load of the power supply is small, i.e., when theload of the charger 11 is small (as in the cases of current-consumptionsaving mode), the standby signal is changed to HIGH so as to performcharging with a massive current. This shortens the charge time.

In the construction described above, the PMOS transistor 21 that canonly be set to either a fully conductive state or a fully nonconductivestate is provided separately from the MOS transistor 71 that can be setto any state in a range between a fully conductive state and a fullynonconductive state. This makes it possible to use an MOS transistorsuitable for a desired operation. If only the PMOS transistor 21 isprovided, the turning on of the PMOS transistor 21 when the voltage ofthe lithium-ion battery 24 is very low causes an excessive current toflow, which may destroy the PMOS transistor 21. In the construction ofFIG. 7, the presence of the PMOS transistor 71 provides a function toprecharge the lithium-ion battery 24 before the PMOS transistor 21 isturned on. This provides an advantage in that excessive heating of thePMOS transistor 21 is prevented. That is, the PMOS transistor 71provides dual functions, i.e., the function to stabilize the inputvoltage V+ according to the invention and the function to precharge thelithium-ion battery 24.

FIG. 8 is a circuit diagram showing the construction of a sixthembodiment of the charge control circuit according to the presentinvention. In FIG. 8, the same elements as those of FIG. 5 are referredto by the same numerals, and a description thereof will be omitted.

In a charge control circuit of FIG. 8, a current monitoring circuit 80is provided in place of the current detector 50, compared with theconstruction of the charge control circuit of FIG. 5. The currentmonitoring circuit 80 receives voltages appearing at opposite ends ofthe current detecting resistor Rs and a voltage VD appearing at one endof a thermistor 81. The thermistor 81 and a resistor R15 are connectedin series, and are situated between a voltage VTH3 and a groundpotential. The thermistor 81 has such characteristics that itsresistance decreases at high temperature, and increases at lowtemperature. As the PMOS transistor 21 generates heat by consumingelectric power, the resistance of the thermistor 81 changes, causing achange in the voltage VD.

The current monitoring circuit 80 includes amplifiers 82 and 83 and areference-voltage source 84. The amplifier 83 detects a voltage dropproduced by the charge current flowing through the current detectingresistor Rs, and supplies a potential VE responsive to the amount of thecharge current to the inversed input terminal of the amplifier 82. Afirst non-inverted input terminal of the amplifier 82 receives areference voltage from the reference-voltage source 84, and a secondnon-inverted input terminal receives the potential VD responsive to theresistance of the thermistor 81. Among the two non-inverted inputs ofthe amplifier 82, one having a lower potential is given priority forcomparison with VE. That is, VD is compared with VE if VD is smallerthan the reference potential, and the reference potential is comparedwith VE if the reference potential is smaller than VD.

At low temperature the resistance of the thermistor 81 is large, so thatthe potential VD is higher than the reference potential. In this case,VE is compared with the reference potential, resulting in the sameoperation as in the case of the construction shown in FIG. 5. The chargecurrent can thus be kept constant. Also, control by the input voltagedetecting circuit 31A and the drive circuit 32A keeps the input voltageV+ constant.

As the PMOS transistor 21 generates heat and becomes high temperature,the resistance of the thermistor 81 drops, resulting in the potential VDbeing lower than the reference potential. In this case, VE is comparedwith VD. As VD becomes lower than VE due to a temperature rise, theoutput of the amplifier 82 drops, which increases the gate voltage ofthe PMOS transistor 21. Consequently, the ON resistance of the PMOStransistor 21 becomes large, with a resultant decrease in the chargecurrent. Conversely, as VD becomes higher than VE due to a temperaturedrop, the output of the amplifier 82 rises, which decreases the gatevoltage of the PMOS transistor 21. Consequently, the ON resistance ofthe PMOS transistor 21 becomes small, with a resultant increase in thecharge current. In this manner, the charge current is decreased inresponse to a temperature rise, and is increased in response to atemperature drop. This makes it possible to ensure a sufficient chargecurrent while keeping the heat generation of the PMOS transistor 21below a predetermined temperature.

Further, the present invention is not limited to these embodiments, butvarious variations and modifications may be made without departing fromthe scope of the present invention.

1. A circuit for controlling charging, comprising: a transistor provided on a charging path between a position of a charging terminal and a position of a battery; an input voltage detecting circuit configured to detect a potential of a point on the charging path coupled to the charging terminal's side of said transistor; and a drive circuit configured to control an ON resistance of said transistor between a conductive state and a nonconductive state in response to the potential detected by said input voltage detecting circuit.
 2. The circuit as claimed in claim 1, wherein said drive circuit makes said transistor substantially fully nonconductive in response to a detection of overcharging.
 3. The circuit as claimed in claim 1, further comprising a circuit configured to make said transistor substantially fully conductive in response to a signal supplied from an exterior.
 4. The circuit as claimed in claim 1, further comprising a current detector configured to detect a charge current flowing through the charging path, wherein said drive circuit controls the ON resistance of said transistor in response to the charge current detected by said current detector.
 5. The circuit as claimed in claim 1, further comprising: a first circuit configured to detect a voltage drop across said transistor; a second circuit configured to detect a charge current flowing through the charging path; and a third circuit configured to obtain a product of the voltage drop detected by said first circuit and the charge current detected by said second circuit, wherein said drive circuit controls the ON resistance of said transistor in response to the product obtained by said third circuit.
 6. The circuit as claimed in claim 1, further comprising: another transistor situated on the charging path in parallel with said transistor; and a circuit configured to make said another transistor substantially fully conductive in response to a signal supplied from an exterior.
 7. The circuit as claimed in claim 1, further comprising: a temperature detecting device; and a temperature detecting circuit, wherein said drive circuit controls the ON resistance of said transistor in response to an output of said temperature detecting circuit.
 8. The circuit as claimed in claim 1, implemented as a semiconductor device.
 9. The circuit as claimed in claim 1, wherein said drive circuit controls the ON resistance of said transistor as a continuous resistance value.
 10. A battery pack, comprising: a charge control circuit; and a battery configured to be charged through a charging path, wherein said charge control circuit includes: a transistor provided on the charging path between a position of a charging terminal and a position of said battery; an input voltage detecting circuit configured to detect a potential of a point on the charging path coupled to the charging terminal's side of said transistor; and a drive circuit configured to control an ON resistance of said transistor between a conductive state and a nonconductive state in response to the potential detected by said input voltage detecting circuit.
 11. An electronic apparatus, comprising: a battery pack including a charge control circuit and a battery configured to be charged through a charging path; a charger having an input terminal receiving a direct-current voltage and an output terminal coupled to said battery pack, and configured step down the direct-current voltage received at the input terminal for output to the output terminal; a DC-DC converter coupled to the output terminal of said charger; and an electronic circuit coupled to an output of said DC-DC converter, wherein said charge control circuit includes: a transistor provided on the charging path between a position of a charging terminal and a position of said battery; an input voltage detecting circuit configured to detect a potential of a point on the charging path coupled to the charging terminal's side of said transistor; and a drive circuit configured to control an on resistance of said transistor between a conductive state and a nonconductive state in response to the potential detected by said input voltage detecting circuit.
 12. The electronic apparatus as claimed in claim 11, wherein said charge control circuit further includes a circuit configured to make said transistor substantially fully conductive in response to a signal indicative of a standby mode of said electronic circuit.
 13. A method of controlling charging, comprising the steps of: detecting a potential at a first position on a charging path for charging a battery; and controlling an ON resistance of a transistor between a conductive state and a nonconductive state, said transistor situated on the charging path at a second position closer to the battery than the first position is.
 14. The method as claimed in claim 13, wherein said step of controlling the ON resistance controls the ON resistance of said transistor as a continuous resistance value.
 15. A circuit for controlling charging, comprising: an input voltage detecting circuit configured to detect a potential of a charging terminal on a charging path for charging a battery; and a drive circuit configured to keep the potential of the charging terminal substantially constant in response to the detected potential.
 16. A circuit for controlling charging, comprising: an input voltage detecting circuit configured to detect a potential of a charging terminal on a charging path for charging a battery; and a drive circuit configured to prevent the potential of the charging terminal from clamping to a potential of the battery in response to the detected potential.
 17. A method of controlling charging, comprising: detecting a potential of a charging terminal on a charging path for charging a battery; and keeping the potential of the charging terminal substantially constant in response to the detected potential.
 18. A method of controlling charging, comprising: detecting a potential of a charging terminal on a charging path for charging a battery; and preventing the potential of the charging terminal from clamping to a potential of the battery in response to the detected potential. 